Dr Bruce Sham

Biography

Bruce Sham received the Bachelor degree (Computer Engineering) and MPhil. degree from the Chinese University of Hong Kong in 2000 and 2002 respectively, and received the PhD. degree from the same university in 2006. He began his research work on digital design during the final year project as an undergraduate which focused on improving the performance, reducing the logic complexity of the system and, hence, power consumption. He has worked as an Electronic Engineer on the FPGA applications of motion control system and system security with cryptography in ASM Pacific Technology Ltd (HK). During the years at the Hong Kong Polytechnic University, he has also engaged in various University projects for the commercialization of technology, in particular, a few optical communication projects which are in collaboration with Huawei. He also worked on physical design of VLSI design automation. He was invited to work at Synopsys, Inc (Shanghai) in the summer of 2005 as a Visiting Research Engineer. He also obtained the Best Paper Award in ISQED 2013 and the Best Paper Award in ATC 2015. He is now working at The University of Auckland as Lecturer.

Research | Current

  1. Hardware Acceleration (using FPGA) of Digital Systems includes: Genomic Analysis, Neural Network and Telecommunication

  2. Software Development on Physical design of VLSI includes: Floorplanning, Placement, Routing, Clock planning and Power management

Areas of expertise

  1. Digital Design
  2. Design Automation of VLSI

Selected publications and creative works (Research Outputs)

  • Lu, Q., Sham, C. W., & Lau, F. C. M. (2016). On using the cyclically-coupled QC-LDPC codes in future SSDs. 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 625-628. Jeju, South Korea. 10.1109/APCCAS.2016.7804048
  • Lu, Q., Fan, J., Sham, C. W., Tam, W. M., & Lau, F. C. M. (2016). A 3.0 Gb/s Throughput Hardware-Efficient Decoder for Cyclically-Coupled QC-LDPC Codes. IEEE Transactions on Circuits and Systems I: Regular Papers, 63 (1), 134-145. 10.1109/TCSI.2015.2510619
    URL: http://hdl.handle.net/2292/32894
  • Lu, Q., Sham, C. W., & Lau, F. C. M. (2015). An architecture-algorithm co-design of artificial intelligence for Trax player. 2015 International Conference on Field Programmable Technology (FPT), 264-267. Queenstown, New Zealand. 10.1109/FPT.2015.7393120
  • Lu, Q., Shen, Z., Sham, C. W., & Lau, F. C. M. (2015). A parallel-routing network for reliability inferences of single-parity-check decoder. 2015 International Conference on Advanced Technologies for Communications (ATC), 127-132. Ho Chi Minh City, Vietnam. 10.1109/ATC.2015.7388304
  • Sham, C.-W., Chen, X., Lau, F., Zhao, Y., & Tam, W. (2013). A 2.0 Gb/s throughput decoder for QC-LDPC convolutional codes. IEEE Transactions on Circuits and Systems I: Regular Papers, 60 (7), 1857-1869. 10.1109/TCSI.2012.2230506
  • Lu, J., & Sham, C.-W. (2013). LMgr: A low-M emory global router with dynamic topology update and bending-aware optimum path search. Proceedings of the 14th International Symposium on Quality Electronic Design ISQED 2013, 231-238. Santa Clara, CA, USA: IEEE. 10.1109/ISQED.2013.6523615
    URL: http://hdl.handle.net/2292/32936
  • Lu, J., Chow, W. K., & Sham, C. W. (2012). Fast Power- and Slew-Aware Gated Clock Tree Synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20 (11), 2094-2103. 10.1109/TVLSI.2011.2168834
  • Lu, J., Chow, W.-K., Sham, C.-W., & Young, E. F. Y. (2010). A dual-MST approach for clock network synthesis. 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 467-473. Taipei, Taiwan. 10.1109/ASPDAC.2010.5419838

Contact details

Primary office location

SCIENCE CENTRE 303S - Bldg 303S
38 PRINCES ST
AUCKLAND 1010
New Zealand

Social links

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