Dr Bruce Sham


Bruce Sham received the Bachelor degree (Computer Engineering) and MPhil. degree from the Chinese University of Hong Kong in 2000 and 2002 respectively, and received the PhD. degree from the same university in 2006. He began his research work on digital design during the final year project as an undergraduate which focused on improving the performance, reducing the logic complexity of the system and, hence, power consumption. He has worked as an Electronic Engineer on the FPGA applications of motion control system and system security with cryptography in ASM Pacific Technology Ltd (HK). During the years at the Hong Kong Polytechnic University, he has also engaged in various University projects for the commercialization of technology, in particular, a few optical communication projects which are in collaboration with Huawei. He also worked on physical design of VLSI design automation. He was invited to work at Synopsys, Inc (Shanghai) in the summer of 2005 as a Visiting Research Engineer. He also obtained the Best Paper Award in ISQED 2013 and the Best Paper Award in ATC 2015. He is now working at The University of Auckland as Lecturer.

Research | Current

  1. Digital design of the computation and communication systems
    1. Improvement of the performance
    2. Reducing the logic complexity of the system
    3. Reducing the power consumption
  2. Physical design of VLSI We make use of design automation techniques to enhance the performance and to improve manufacturability. Numerous important problems in physical design are studied and are going to be solved such as
    1. Floorplanning
    2. Placement
    3. Routing
    4. Clock planning
    5. Power management

Areas of expertise

  1. Digital Design
  2. Design Automation of VLSI

Selected publications and creative works (Research Outputs)

  • Lu, Q., Sham, C. W., & Lau, F. C. M. (2016). On using the cyclically-coupled QC-LDPC codes in future SSDs. 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 625-628. Jeju, South Korea. 10.1109/APCCAS.2016.7804048
  • Lu, Q., Fan, J., Sham, C. W., Tam, W. M., & Lau, F. C. M. (2016). A 3.0 Gb/s Throughput Hardware-Efficient Decoder for Cyclically-Coupled QC-LDPC Codes. IEEE Transactions on Circuits and Systems I: Regular Papers, 63 (1), 134-145. 10.1109/TCSI.2015.2510619
    URL: http://hdl.handle.net/2292/32894
  • Lu, Q., Sham, C. W., & Lau, F. C. M. (2015). An architecture-algorithm co-design of artificial intelligence for Trax player. 2015 International Conference on Field Programmable Technology (FPT), 264-267. Queenstown, New Zealand. 10.1109/FPT.2015.7393120
  • Lu, Q., Shen, Z., Sham, C. W., & Lau, F. C. M. (2015). A parallel-routing network for reliability inferences of single-parity-check decoder. 2015 International Conference on Advanced Technologies for Communications (ATC), 127-132. Ho Chi Minh City, Vietnam. 10.1109/ATC.2015.7388304
  • Yao, H., Yang, F., Cai, Y., Zhou, Q., & Sham, C.-W. (2015). SIAR: Customized real-time interactive router for analog circuits. Integration, the VLSI Journal, 48, 170-182. 10.1016/j.vlsi.2014.03.001
  • Yao, H., Gao, Q., Cai, Y., Zhou, Q., & Sham, C.-W. (2014). Length matching in detailed routing for analog and mixed signal circuits. Microelectronics Journal, 45 (6), 604-612. 10.1016/j.mejo.2014.04.007
  • Chow, W.-K., Li, L., Young, E. F. Y., & Sham, C.-W. (2014). Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach. Integration, the VLSI Journal, 47 (1), 105-114. 10.1016/j.vlsi.2013.08.001
  • Sham, C.-W., Chen, X., Lau, F. C. M., Zhao, Y., & Tam, W. M. (2013). A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes. IEEE Transactions on Circuits and Systems I: Regular Papers, 60 (7), 1857-1869. 10.1109/TCSI.2012.2230506

Contact details

Primary location

Level 5, Room 588
New Zealand

Social links

Web links